module uart_tx_tb(
input 				clk,
					nreset,
					en_tx,
					baud_set,
input	[7:0]		din,
output 	reg 		tdc,//data buffer full
output 				txd
				);
reg		[9:0] 		shift;
reg		[3:0] 		state;
reg		[11:0]		cnt;

wire	[11:0]		baud;


	
parameter		BAUD_115200 = 12'd216, 	//baud rate 115200//25Mhz
				BAUD_19200 = 12'd1301,  //baud rate 19200
				BAUD_9600  = 12'd2603;  //baud rate 9600



assign txd = shift[0];

assign baud = baud_set ? BAUD_9600 : BAUD_19200;
	
always@(posedge clk or negedge nreset)
if(nreset==0)
	begin
		state<=0;
		shift<=10'b1;
		cnt <= 0;
	end 
else 
	case(state)
	4'b0000:begin
	       if(en_tx)
				begin 
				shift[8:1]<=din;shift[0]<=1'b0;cnt <= 0;
				shift[9]<=1'b1; state<=1;
				end 
			else 
				state <= 4'd0;
				tdc <= 0;
				end
	4'b0001:if(cnt == baud) //data 0
				begin 
				shift<=shift>>1;state<=2;cnt <= 0;
				shift[9]<=1'b1; 
				end 
			else 
				cnt <= cnt + 1;
	4'b0010:if(cnt == baud)//data 1
				begin 
				shift<=shift>>1;state<=3;cnt <= 0;
				shift[9]<=1'b1; 
				end 
			else 
				cnt <= cnt + 1;
	4'b0011:if(cnt == baud)//data 2
				begin 
				shift<=shift>>1;state<=4;cnt <= 0;
				shift[9]<=1'b1; 
				end 
			else 
				cnt <= cnt + 1;
	4'b0100:if(cnt == baud)//data 3
				begin 
				shift<=shift>>1;state<=5;cnt <= 0;
				shift[9]<=1'b1; 
				end 
			else cnt <= cnt + 1;
	4'b0101:if(cnt == baud)//data 4
				begin				
				shift<=shift>>1;state<=6;cnt <= 0;
				shift[9]<=1'b1; 
				end 
			else cnt <= cnt + 1;
	4'b0110:if(cnt == baud)//data 5
				begin 
				shift<=shift>>1;state<=7;cnt <= 0;
				shift[9]<=1'b1; 
				end 
			else cnt <= cnt + 1;
	4'b0111:if(cnt == baud)//data 6
				begin 
				shift<=shift>>1;state<=8;cnt <= 0;
				shift[9]<=1'b1; 
				end 
			else cnt <= cnt + 1;
	4'b1000:if(cnt == baud)//data 7
				begin 
				shift<=shift>>1;state<=9;cnt <= 0;
				shift[9]<=1'b1; 
				end 
			else cnt <= cnt + 1;
	4'b1001:if(cnt == baud)//bit end
				begin 
				shift<=shift>>1;state<=10;cnt <= 0;
				shift[9]<=1'b1; 
				end 
			else cnt <= cnt + 1;
	4'b1010:if(cnt == baud)//bit end should last BAUD
				begin 
				state<=0;cnt <= 0;
				tdc <= 1;
				end 
			else cnt <= cnt + 1;
	default:begin cnt <= 0;state<=0;end
	endcase
endmodule 
